1. Field of the Invention
The present invention relates to a method of forming a self-aligned contact hole on a semiconductor wafer, and more particularly, to a method of forming a self-aligned contact hole with a large contact area on a semiconductor wafer.
2. Description of the Prior Art
For years, the self-aligned contact (SAC) etching technology has been widely used in the manufacturing processes for dynamic random access memory (DRAM) and embedded dynamic random access memory (e-DRAM). It is used, for example, when making a contact hole in a DRAM chip through which a memory cell on the DRAM chip connects with a bit line. A small amount of misalignment can be tolerated when using the SAC technology in the prior art method of forming a self-aligned contact hole. However, owing to the increasing integration of semiconductor devices, and the limitation of the width of the spacers of a metal-oxide-semiconductor (MOS) transistor, the prior art method of forming a self-aligned contact hole has a disadvantage that the decreasing contact area results in an increased resistivity of the contact plug.
Please refer to FIG. 1 to FIG. 5. FIG. 1 to FIG. 5 are cross-sectional diagrams of the prior art method of forming a self-aligned contact hole on a semiconductor wafer. Please refer to FIG. 1. A cross-sectional view of a portion of a silicon substrate 12 with a partially completed DRAM cell is shown. A semiconductor wafer comprises the silicon substrate 12 and a shallow, dielectric-filled trench 14 located on the surface of the silicon substrate 12 that isolates the individual device regions. The silicon substrate 12 comprises an array area 20 that comprises an array of memory cells of dynamic random access memory, and a periphery area 30 located on the substrate 12 comprising a control circuit of the DRAM. The array of memory cells in the array area 20 comprises a first gate electrode 16, and a second gate electrode 16 adjacent to the first gate electrode 16. The control circuit in the periphery area 30 comprises at least a third gate electrode 18.
As shown in FIG. 2, in the prior art method the lightly doped drain (LDD) areas 22 that are used to prevent short channel effects are first formed adjacent to the gate electrodes 16, 18. Usually, the gate electrodes 16, 18 are used as part of the implantation mask, and N-type dopant species such as arsenic or phosphorus are implanted into the substrate. Next, a silicon dioxide buffer oxide layer 24, and a silicon nitride layer (not shown in FIG. 2) are sequentially formed on the silicon substrate 12 using a chemical vapor deposition (CVD) process. The buffer oxide layer 24 serves to reduce the thermal stress of the silicon nitride layer. The silicon nitride layer is used to form subsequent spacers 25. The preferred thickness of the buffer oxide layer 24 is typically between 100 to 200 Angstroms. As shown in FIG. 3, after depositing the buffer oxide layer 24 and the silicon nitride layer, an anisotropic dry etching process is used to form the spacers 25 on the walls of opposite sides of the gate electrodes 16, 18.
Referring next to the FIG. 4, an ion implantation process follows to form the source 27 and drain 28 in the periphery area 30, and a subsequent annealing process is used to restore the lattice structure which is damaged by the incident atoms and electrons during the implantation process. Then, a second silicon nitride layer 29, acting as the salicide block mask (SAB) in the formation of a salicide layer 26, is formed over the array area 20 by a CVD process. Furthermore, in order to reduce the contact resistance to the source 27 and drain 28, a silicidation process is performed on the surface of the source 27 and drain 28 to form a silicide layer, wherein titanium and cobalt are typically used as the metal source in the silicidation process.
Referring next to the FIG. 5, an inter-poly dielectric layer 32 is formed on the surface of the semiconductor wafer 10 by a CVD process. Then, a photoresist layer (not shown) is formed on at he surface of the semiconductor wafer 10, and a photo-lithographic process is performed to define the location of the self-aligned contact hole. Finally, a wet etching process is performed to remove the photoresist layer over the contact hole and a self-aligned contact dry etching process is used to complete the self-aligned contact hole 34.
Referring still to FIG. 5, damage to the buffer oxide layer 24 is observed after the self-aligned contact etching process in the prior art. The inter-poly dielectric layer 32 and the buffer oxide layer 24 are both composed of silicon dioxide. Hence, the plasma etches both of the layers during the self-aligned contact etching process.
Please refer to FIG. 6. FIG. 6 is a cross-sectional diagram of the prior art method of forming a polysilicon plug in the self-aligned contact hole. After completing the self-aligned contact hole 34, a polysilicon plug is formed in the contact hole 34 so as to make electrical connections between the circuits and the semiconductor regions. However, the damage to the buffer oxide layer 24 adjacent to the gate electrodes 16, 18 results in contact between the gate and the plug, thereby forming a short circuit after the formation of the polysilicon plug.
As integration of semiconductor devices and the density of memory cells in and on a DRAM chip increase, the contact area 36 at the bottom of the self-aligned contact hole 34 shrinks. A small contact area may result in an undesirable high resistivity, which increases the signal transfer time and energy consumption of a semiconductor device. In order to reduce the contact plug resistivity, it is desirable to make the contact area as large as possible for the DRAM fabrication process.
Unfortunately, the contact area 36 is limited by the thickness of the spacers 25 in the prior art. As shown in FIG. 5, the thickness of the spacers 25 in the periphery area 30 is the same as the spacers 25 in the array area 20 because they are all formed at the same time. The width of the lightly doped drain areas 22 with respect to the thickness of the spacers 25 will significantly influence the electrical properties of a metal-oxide-semiconductor (MOS) transistor in the periphery area 30. Thin spacers result in narrow lightly doped drain areas, which can cause serious thermal electron problems in the MOS transistor. Consequently, it is impossible to increase the contact area 36 by reducing the thickness of the spacers 25 in the array area 20 in the prior art. A solution to this problem is of considerable importance.
The main disadvantage of the prior art method of forming a self-aligned contact hole is that it cannot provide sufficient contact area 36 to the source 27 and drain 28 in the array area 20. This results in a high resistivity that reduces the performance of the semiconductor device.